A national, hardware-agnostic stack that takes quantum programs from Python, C++ or Rust down to the pulses that drive the qubits, and runs them alongside high-performance computing.
Quantum computers will work beside supercomputers as accelerators. Using them takes software that compiles one program for different quantum hardware, runs it reliably and coordinates it with HPC.
SQS² builds that layer as national infrastructure: vendor-neutral, based on open standards, and a stack national institutions can operate, extend and trust.
"We are building a sovereign AI-powered quantum software stack—deeply integrated with HPC—to accelerate the next era of national innovations in quantum computing"
A sovereign stack lets national institutions adopt quantum computing on their own terms and builds national expertise in quantum software, in support of Vision 2030 goals in energy, materials, finance and logistics.
Five layers lower a program from the user’s code to the pulses that drive the qubits. Figure 1 follows one program through them, and Figure 2 shows the middleware that links them to HPC and to classical and quantum hardware.
OPENQASM 3.0;include "stdgates.inc";qubit[2] q;bit[2] c;h q[0]; // superpositioncx q[0], q[1]; // entanglec = measure q;
A Bell-state program in OpenQASM 3.
Designing, testing and benchmarking quantum and hybrid algorithms for practical problems, including but not limited to:
Open intermediate representations, OpenQASM 3 and QIR, let one program target devices from different vendors.
Hybrid quantum–classical jobs run through the schedulers HPC centres already use, such as Slurm.
Machine learning for compilation, calibration, readout and error mitigation.
Coordinating several connected quantum processors as one resource.
Protecting quantum programs, devices and remote access: secure job submission, isolation between users on shared machines, and trustworthy results.
SQS² is developed and tested on laboratory hardware, from cryogenic systems to control electronics, and targets two qubit technologies.
Microwave circuits on a chip, cooled to about 10 mK. Each gate is a shaped pulse tens of nanoseconds long, so the lowest layer of the stack works in pulses, not gates.
Single atoms held in optical tweezers. Loading is random, so atoms are rearranged into a defect-free register before each run.
A dilution refrigerator cools the processor in stages from 50 K to 10 mK. Controllers and FPGA boards generate and read the pulses in real time.
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